1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to vertical channel flash EEPROM memory devices.
2. Description of Related Art
An EPROM (Erasable Programmable Read Only Memory) provides long term storage of charge of a floating gate doped polysilicon electrode in a device such as an FET (Field Effect Transistor) device. In a MOSFET PROM device source/drain regions are formed on either side of a channel in a semiconductor substrate below a tunnel oxide dielectric layer and a floating gate doped polysilicon electrode, above which are a interpolysilicon dielectric layer and a control gate doped polysilicon electrode. Usually the EPROM is programmable (stores data) electrically by injection of hot electrons into the floating gate electrode. An EPROM can be erased, with utltraviolet light. An EPROM erased electrically is an EEPROM device described next.
An EEPROM (Electrically Erasable Programmable Read Only Memory) device includes an array of memory cells which can be erased electrically.
In a flash EEPROM device memory cells can be erased electrically, simultaneously with an electrical erase signal, instantaneously (within a few seconds) by Fowler-Nordheim tunneling of the charge from the floating gate into the drain region.
Some disadvantages of currently available flash memory cells are as follows:
1. A large cell area is required for split-gate flash memory cells available heretofore. PA1 2. There has been a punch-through issue for split-gate flash memory cells available in the past. PA1 3. There is a planarization issue for flash memory cells available prior to this invention. PA1 1. A unit cell can take less cell area but with more channel area. PA1 2. Because the floating gate electrode is located under the wafer surface, the step height of the cell gate electrode stack is much lower than that of a traditional gate electrode stack. As a result following etch steps, (e.g. cell gate electrode etching and contact hole etching) are far easier. PA1 3. The source side junction which is used for source side injection, is patterned, in part, by the depth of the source-line diffusion process. As a result, the floating gate voltage V.sub.FG can be easily dominated by the source side voltage to inject electrons from the channel into the floating gate electrode through the tunnel oxide layer. PA1 4. There is a large control gate to floating gate overlap area for this cell. As a result, this cell can use lower control gate voltage for the erase function, which provides for high efficiency for the source erase function. PA1 5. Because there is a much larger area of the tunnel oxide layer located between the source region and the floating gate electrode than that of the traditional structure, the erasing speed is far faster also.
U.S. Pat. No. 5,045,490 of Esquivel et al. for "Method for Making a Pleated Floating Gate Trench EPROM" shows a method of making a pleated floating gate trench EPROM device.
U.S. Pat. No. 5,313,421 of Guterman et al. for "EEPROM with Split Gate Source Side Injection" shows a method/structure of an EEPROM device including a floating gate and a control gate electrode in a split gate configuration which provides injection of electrons to charge the floating gate near the source side of the channel of the EEPROM device.
U.S. Pat. No. 5,467,305 of Bertin et al. for "Three-Dimensional Direct-Write EEPROM Arrays and Fabrication Methods" shows a three-dimensional EEPROM array formed in a trench.
U.S. Pat. No. 5,595,927 of Chen et al. for "Method for Making Self-Aligned Source/Drain Mask ROM Memory Cell Using Trench Etched Channel" shows a method for making a ROM using an etched trench channel.